1. Field
The present invention relates to a nonvolatile semiconductor memory device in which data write and erase are electrically executed and which has a stacked gate structure, and a method of fabricating the same.
2. Related Art
Nonvolatile semiconductor memory devices such as NAND flash memory devices employ the following configuration. An interelectrode insulating film is provided between a floating gate electrode and a control gate electrode in a film configuration of gate electrodes of memory cell transistors. Transistors other than the memory cell transistors employ the same film configuration as of the memory cell transistors but necessitate no floating gate electrode nor interelectrode insulating films. Accordingly, an opening is formed in the interelectrode insulating film, and the control gate electrode and the floating gate electrode are brought into contact with each other through the opening, whereby a short circuit is caused therebetween.
With progress in the refinement of a pattern defined by a design rule, the width of a word line connecting control gate electrodes of memory cell transistors has been reduced, and an interconnection resistance is increased. Consequently, the forming of a metal silicide film having a lower resistance value has been proposed. Even when a metal silicide film is used, it is suggested that silicide should be made as an alloy of a metal such as nickel (Ni) and polycrystalline silicon for the purpose of realizing low resistance.
However, it is difficult to control progress of silicidation when the siliciding process is carried out after gate electrodes have been formed by stacking films. For example, a memory cell transistor includes a portion which suppresses the progress of silicide reaction. In this case, accordingly, no problem arises regarding as an element characteristic even when the silicide reaction reaches the interelectrode insulating film. However, since an opening is formed in the interelectrode insulating film in transistors other than the memory cell transistor, the silicide reaction progresses via the opening into a polycrystalline silicon film to serve as an underlying floating gate electrode. Consequently, the silicide reaction is anticipated to reach a gate insulating film according to the circumstances. This would result in adverse effects such as deterioration in the reliability of the gate oxide film or variations in a threshold of selective gate transistor, whereupon element characteristics would be adversely affected.
Japanese patent application publication JP-A-2007-207946 discloses means for overcoming the above-noted problem. In this case, an insulating film serving as a stopper is interposed in the opening to control silicidation. However, the interposition of insulating film results in an increase in electrical resistance in a portion to be normally connected electrically. Thus, problems sill need to be overcome regarding element characteristics.